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general description the max16997/max16998 are microprocessor (p) supervisory circuits for high-input-voltage and low- quiescent-current applications. these devices detect downstream circuit failures and provide switchover to redundant circuitry. see the selector guide for the different versions of this product family. the max16997/max16998 family has four independent inputs for reset and watchdog functions. swt and srt inputs independently set the timeout periods of watchdog and reset timers through external capacitors. resetin/ en monitor voltages at respective inputs. a resistive voltage-divider sets the reset threshold. the max16998a/b/d generate two output signals, reset and enable . reset asserts whenever resetin drops below its threshold voltage or when the watchdog timer detects a timing fault at wdi. once asserted, and after all reset conditions are removed, reset remains low for the reset timeout period, t reset , and then goes high. the max16997a generates one output signal ( enable ) based on the voltage level at en and the signal at wdi. the max16997a does not have a reset output. the watchdog is disabled if the voltage at en is below its threshold. the max16997a watchdog timer starts timing when the voltage at en becomes higher than the preset threshold voltage level. each time en rises above the pre - set threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). the max16997/max16998 are available in 8-pin lead(pb)-free max ? packages and are fully specified over the -40c to +125c automotive temperature range. applications automotive industrial features wide 5v to 40v input voltage range 18a quiescent current (typical at +125c) capacitor-adjustable timeout period for watchdog and reset windowed watchdog timer options (max16998b/d) external voltage monitoring (resetin for the max16998a/b/d and en for the max16997a) car battery-compatible en input ttl- and cmos-compatible open-drain outputs 18v maximum open-drain reset output voltage 28v maximum open-drain enable output voltage power-on/power-off reset functionality (max16998a/b/d only) aec-q100 qualified -40c to +125c operating temperature range small (3mm x 3mm) max package wdi narrow pulse immunity 19-4000; rev 4; 3/16 pin configurations appear at end of data sheet. +denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. max is a registered trademark of maxim integrated products, inc. part temp range pin-package max16997 aaua+ -40c to +125c 8 max max16998 aaua+ -40c to +125c 8 max max16998aaua/v+ -40c to +125c 8 max max16998baua+ -40c to +125c 8 max max16998baua/v+ -40c to +125c 8 max max16998daua+ -40c to +125c 8 max max16998daua/v+ -40c to +125c 8 max part watchdog window size (%) enable reset en resetin max16997a 100 max16998a 100 max16998b 50 max16998d 75 max16997/max16998 high-voltage watchdog timers with adjustable timeout delay selector guide ordering information downloaded from: http:///
(all pins referenced to gnd, unless otherwise noted.) in, enable ............................................................-0.3v to +45v wdi, reset , en.....................................................-0.3v to +20v resetin................................................................-0.3v to +20v srt, swt................................................................-0.3v to +12v maximum current (all pins).................................................30ma continuous power dissipation (t a = +70c) 8-pin max (derate 4.8mw/c above +70c)..........387.8mw operating temperature range (t a )...................-40c to +125c junction temperature (t j )................................................+150c storage temperature range..............................-65c to +150c lead temperature (soldering, 10s)...................................+300c (v in = 14v, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units operating voltage range v in 5.0 40.0 v supply current i in t a = -40c to +85c 18 30 a t a = -40c to +125c 18 60 swt ramp current i ramp_swt v swt = 1.0v 450 500 550 na srt ramp current i ramp_srt v srt = 1.0v 410 500 600 na swt/srt ramp threshold voltage v ramp 1.115 1.235 1.363 v reset timer power-on reset input threshold voltage v pon v resetin rising 1.135 1.255 1.383 v v resetin falling 1.115 1.235 1.363 resetin input leakage current i lpon v resetin = 2v 0.1 a reset output low voltage v olrst reset asserted, i sink = 1ma 0.9 v v in = 1.1v, i sink = 160a, reset asserted 0.4 reset asserted, i sink = 0.4ma 0.4 reset leakage current i lkgr v reset = 20v, reset not asserted 0.1 a enable output low voltage v olen enable asserted, i sink = 5ma 0.4 v enable leakage current i lkge v enable = 14v, enable not asserted 0.1 a minimum reset timeout period t resetmin c srt = 390pf (note 3) 1 ms reset timeout period t reset c srt = 2000pf (note 3) 5 ms maximum reset time period t resetmax c srt = 47nf 116.09 ms reset to enable delay t redl 1.5 s resetin to reset delay t rrdl resetin falling below v pon to reset falling edge 1 s max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the devi ce. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics junction-to-case thermal resistance ( jc .................... 42c/w junction-to-ambient thermal resistance ( ja ) ............. 206.3c/w (note 1) package thermal characteristics downloaded from: http:///
(v in = 14v, t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 2) note 2: r reset and r enable are external pullup resistors for open-drain outputs. connect r reset and r enable to a minimum 2.5v voltage. connect r reset to a maximum voltage of 18v and connect r enable to a maximum voltage of 28v. note 3: calculated based on v ramp = 1.235v and i ramp = 500na. note 4: wdi pulses narrower than 1s will be ignored. wdi pulses wider than 6.5s will be recognized. note 5: not production tested, guaranteed by design. (c swt = c srt = 1500pf, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units watchdog timer wdi input threshold v ih 2.25 v v il 0.9 wdi input hysteresis wdi hyst 200 mv wdi minimum pulse width t wdimin (note 4) 6.5 s wdi input current i wdi wdi = 0 or 14v 0.1 a minimum watchdog timeout period t wpmin c swt = 680pf (note 3) 6.8 ms watchdog timeout period t wp c swt = 1200pf (note 3) 12 ms maximum watchdog timeout t wpmax c swt = 22nf 217.36 ms watchdog window d wdi max16998b 45 50 55 %t wp max16998d 67.5 75 82.5 wdi to enable output delay start from wdi third wrong trigger 100 s reset pullup resistor supply voltage (note 5) 2.25 2.5 18.00 v enable pullup resistor supply voltage (note 5) 2.25 2.5 28.00 v watchdog timeout period vs. c swt max16997/98 toc02 c swt (nf) watchdog timeout period (ms) 100 10 1 10 100 1000 10,000 1 0.1 1000 i ramp = 500na supply current vs. supply voltage max16997/98 toc03 supply voltage (v) supply current (a) 40 30 10 20 12 14 16 18 2220 24 2610 0 50 reset and enable not asserted reset timeout period vs. c srt max16997/98 toc01 c srt (nf) reset timeout period (ms) 100 10 1 1 10 100 1000 10,000 0.1 0.1 1000 i ramp = 500na max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) typical operating characteristics downloaded from: http:///
(c swt = c srt = 1500pf, t a = +25c, unless otherwise noted.) resetin/en threshold voltage vs. temperature max16997/98 toc05 temperature (c) resetin/en threshold voltage (v) 110 95 65 80 -10 5 20 35 50 -25 1.13 1.15 1.18 1.20 1.23 1.25 1.28 1.30 1.33 1.351.10 -40 125 rising falling resetin/en threshold voltage vs. supply voltage max16997/98 toc06 supply voltage (v) resetin/en threshold voltage (v) 36 32 24 28 12 16 20 8 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.501.00 4 40 rising falling resetin to reset delay vs. temperature max16997/98 toc07 temperature (c) resetin to reset delay (ms) 110 95 -25 -10 5 35 50 65 20 80 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 -40 125 resetin from 2v to 0v 100mv overdrive 50mv overdrive resetin/watchdog period vs. supply voltage max16997/98 toc08 supply voltage (v) reset/watchdog timeout period (ms) 36 32 8 12 16 24 20 28 1 2 3 4 5 6 7 80 4 40 watchdog timeoutperiod (c swt = 680pf) reset timeoutperiod (c srt = 680pf) resetin/watchdog period vs. supply voltage max16997/98 toc09 supply voltage (v) reset/watchdog timeout period (ms) 36 32 24 28 12 16 20 8 20 30 40 50 60 70 80 90 100 110 10 4 40 watchdog timeoutperiod (c swt = 10nf) reset timeoutperiod (c srt = 10nf) i ramp vs. temperature max16997/98 toc10 temperature (c) i ramp (na) 110 95 65 80 -10 5 20 35 50 -25 475 480 485 490 495 500 505 510 515 520470 -40 125 supply current vs. temperature max16997/98 toc04 temperature (c) supply current (a) 110 95 65 80 -10 5 20 35 50 -25 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.015.0 -40 125 reset and enable not asserted reset output voltage vs. sink current max16997/98 toc11 sink current (ma) reset output voltage (v) 2.5 2.0 1.5 1.0 0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3.0 0 enable output voltage vs. sink current max16997/98 toc12 sink current (ma) enable output voltage (v) 25 20 5 10 15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0 30 maxim integrated 4 www.maximintegrated.com max16997/max16998 high-voltage watchdog timers with adjustable timeout delay typical operating characteristics (continued) downloaded from: http:///
pin name function max16997a max16998a/b/d 1 1 in power-supply input. bypass in to gnd with a 0.1f capacitor. 2 en high-impedance input to the enable comparator. depending on the voltage level at en, the internal watchdog timer is turned on or off (see the en input section). 3, 7 n.c. no connection. not internally connected. 4 4 swt watchdog timeout adjustment input. connect a capacitor between swt and gnd to set the basic watchdog timeout period. connect swt to ground to disable the watchdog timer function. see the selecting the watchdog timeout capacitor section. 5 5 gnd ground 6 6 wdi watchdog input. max16997a/max16998a (timeout watchdog): two consecutive wdi falling edges must occur at wdi within the watchdog timeout period or reset asserts. the watchdog timer clears when a falling edge occurs on wdi or whenever reset is asserted. enable asserts if three consecutive watchdog timeout periods have expired without a falling edge at wdi. wdi is a high-impedance input. leaving wdi unconnected will cause improper operation of the watchdog timer. max16998b/d (window watchdog): wdi falling transitions within periods shorter than the closed window width or longer than the basic watchdog timeout period force reset to assert low for the reset timeout period. the watchdog timer begins to count after reset is deasserted. the watchdog timer clears when a wdi falling edge occurs or whenever reset is asserted. enable asserts if three consecutive watchdog timeout periods have expired without a falling edge at wdi. wdi is a high-impedance input. leaving wdi unconnected will cause improper operation of the watchdog timer. 8 8 enable open-drain enable output. enable asserts when three consecutive wdi faults occur. enable remains low until three consecutive good wdi falling edges occur. enable does not assert if the voltage at resetin (en) is below its threshold. these devices are guaranteed to be in correct enable output logic state when v in remains greater than 1.1v. 2 resetin reset input. high-impedance input to the reset comparator. when v resetin falls below 1.235v, reset asserts. reset remains asserted as long as v resetin is low and for the reset timeout period after resetin goes high. connect v resetin to the center point of an external resistive divider to set the threshold for the externally monitored voltage. connect resetin to a deined voltage logic-level. 3 srt reset timeout adjustment input. connect a capacitor between srt and gnd to set the reset timeout period. see the selecting the reset timeout capacitor section. 7 reset open-drain reset output. reset asserts whenever resetin drops below the selected reset threshold voltage (v pon ). reset remains low for the reset timeout period after all reset conditions are removed, and then goes high. reset asserts for a period of t reset whenever a wdi fault occurs. connect reset to a pullup resistor connected to a voltage higher than 2.5v (typ). max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 5 pin coniguration downloaded from: http:///
in resetin (max16998) en (max16997) wdi reset enable swt srt (max16998) v bg v bg i ramp preg buffer max16997a/ max16998a/b/d logic gnd v bg i ramp max16997/max16998 max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 6 functional diagram downloaded from: http:///
figure 1. max16997a timing diagram figure 2. max16998a timing diagram v en v hyst t wp initial t wp initial = watchdog timeout period x 8 t wp = watchdog timeout period t wdi = wdi trigger period 3 consecutive t wp without trigger enable goes low 3 consecutive watchdog trigger (wdi) enable goes active high t wp t wd t wp t wp 1 2 3 1 2 3 t wp t wp t wdi t wdi t wdi t wdi v pon wdi enable v resetin v hyst t reset = reset timeout period t wp = watchdog timeout period t wdi = wdi trigger period 3 consecutive resets enable goes active low 3 consecutive watchdog trigger (wdi) enable goes active high 1 1 2 2 3 3 t wp t wdi t wp t wp t wp t wdi t wdi t wdi t reset v pon wdi enable reset max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 7 timing diagrams downloaded from: http:///
figure 3. max16998b/d timing diagram figure 4. resetin, reset , v in , enable , and wdi voltage monitoring v resetin v hyst proper watchdog trigger resets the internal enable counter t reset = reset timeout period t ow = t open window t cw = t closed window t wp = t cw + t ow t wdi = wdi trigger period 3 consecutive resets enable goes active low 3 consecutive watchdog trigger (wdi) enable goes active high t wp 1 2 3 1 2 3 t wdi t reset t ow t cw t wp t wp t wp t wdi t wdi t wdi v pon wdi enable reset v hyst t ow t = 0 t cw t wp t reset t cw t wdi t wp t cw t wdi t wp t wp enable does not get asserted if the voltage at resetin is below its threshold. the watchdog timer clears whenever reset is asserted. t rrdl t wdi t wdi t wdi t wdi t wdi t wdi t wdi t wdi v resetin v pon wdi 1.1v v in = enable reset t reset t reset max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 8 timing diagrams (continued) downloaded from: http:///
detailed description the max16997/max16998 are p supervisory circuits for high-input-voltage and low-quiescent-current applications. these devices improve system reliability by monitoring the sub-system for software code execution errors. the max16997a/max16998a/b/d detect downstream circuit failures, and provide switchover to redundant circuitry. these devices provide complete adjustability for reset and watchdog functions. the max16998a/b/d generate two output signals, reset and enable , that depend on the voltage level at resetin and the signal at wdi. reset asserts whenever resetin drops below the selected reset threshold voltage. reset remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. reset also asserts for a period of t reset whenever a wdi fault occurs. the max16997a generates one output signal ( enable ) based on the voltage level at en and the signal at wdi. the max16997a/max16998a provide watchdog timeout adjustability with an external capacitor. the max16998a asserts reset when two consecutive wdi falling edges do not occur within the watchdog timeout period. this device also asserts enable if three consecutive watch - dog timeout periods have elapsed without a falling edge at wdi. enable remains low until three consecutive good wdi falling edges occur. enable does not assert if the voltage at resetin (en) is below its threshold. for the max16997a, the watchdog timer starts timing if the volt - age at en is higher than a preset threshold level. each time the voltage at en rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). other than described above, the max16997a behaves the same as the max16998a. the max16998b/max16998d contain a window watch - dog timer that looks for activity outside an expected window of operation. the window size is factory-set to 50% (max16998b) or 75% (max16998d) of the adjusted watchdog timeout period. reset output ( reset ) (max16998a/b/d) the reset output is typically connected to the reset input of the c to start or restart it in a known state. the max16998a/b/d provide an active-low open-drain reset logic to prevent code execution errors. for the max16998a/b/d, reset asserts whenever resetin drops below the selected reset threshold volt - age (v pon ). reset remains low for the reset timeout period after resetin exceeds the selected threshold voltage, and then goes high. the max16998a asserts reset for a period of t reset when two consecutive wdi falling edges do not occur within the adjusted watchdog timeout period. the max16998b/d also assert reset for a period of t reset when a wdi falling edge does not occur within the open window period. anytime reset asserts, the watchdog timer clears. at the end of the reset timeout period, reset goes high, and the watchdog timer is restarted from zero (see the selecting the watchdog timeout capacitor section). enable output ( enable ) if the c fails to operate correctly (e.g., the software execu - tion is stuck in a loop), wdi does not trigger any more and reset pulls low, resetting the c. if the c does not work properly in the next loop either, the device asserts reset again. after three watchdog timeout periods elapse with no falling edges at wdi, enable asserts and flags a backup circuit that can take over the operation. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog timeout occur. enable does not assert if the voltage at resetin (en) is below its threshold. these devices are guaran - teed to be in correct enable output logic state when v in remains greater than 1.1v. power-on/power-off sequence figure 5 shows the power-up and power-down sequence for reset and enable for the max16998a/b/d. on power-up, once v in reaches 1.1v, reset goes logic-low. as resetin rises, reset remains low. when resetin rises above v pon , the reset timer starts and reset remains low. when the reset timeout period ends, reset goes high. on power-down, once resetin goes below v pon , reset goes low and remains low until v in drops below 1.1v. figure 6 shows the detailed power-up sequence for the max16998a/b/d. max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 9 downloaded from: http:///
figure 5. power-on reset and power-down reset for the max16998a/b/d figure 6. detailed power-up sequence for the max16998a/b/d v hyst t reset t wp t cw t wdi t wp t cw t wdi t wp the three consecutive reset could be caused by three timeouts as shown here or by three wdi falling edge outside the open window, or a combination of any reset conditions except v resetin drops too low. t ow t = 0 t cw t wp t reset t reset t reset t wdi t wdi t wdi t wdi t wdi t wdi t wdi t wdi v resetin v in v in = 1.1v v pon wdi enable reset reset wdt clears and starts counting from o wdi t wp t wp v hyst v in = 1.1v v pon v in = v enable v resetin v reset t reset max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 10 downloaded from: http:///
resetin input (max16998a/b/d) the max16998a/b/d monitor the voltage at resetin using an adjustable reset threshold, set with an external resistive divider (see figure 7 ). reset asserts when v resetin is below 1.235v. use the following equations to calculate the externally monitored voltage (v cc ). 1 th pon 2 r vv 1 r ?? = + ???? where v th is the desired reset threshold voltage, and v pon = 1.235v. to simplify the resistor selection, choose a value for r 2 (< than 1m) and calculate r 1 . th 12 pon v rr 1 v ?? = ? ?? ?? en input the max16997a provides a high-impedance input (en) to the enable comparator. based on the voltage level at en, the watchdog timer is turned on or off. the watchdog timer starts timing if the voltage level at en is higher than a preset threshold voltage (v pon ). each time the voltage at en rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t wp ). watchdog timer max16997a the watchdog circuit monitors the cs activity. for the max16997a, the watchdog timer starts timing once the voltage at en is higher than a preset threshold voltage. enable asserts if three consecutive watchdog timeout periods have elapsed without a falling edge at wdi. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog timeout period occur. each time the voltage at en rises from below to above the preset threshold voltage, the first watchdog timeout period extends by a factor of 8 (8 x t wp ). if a wdi falling edge occurs during that time, then the watchdog timeout period is immediately switched over to a single t wp . if no watchdog falling edge occurs during this prolonged watchdog timeout period, enable goes low at the end of this period and stays low. after this, the first falling edge at wdi switches the watchdog timeout period to a single t wp . see figure 1 . the max16997a watchdog timeout period (t wp ) is adjustable by a single capacitor at swt. max16998a the max16998a asserts reset when two consecutive wdi falling edges do not occur within the adjusted watch - dog timeout period (t wp ). reset remains asserted for the reset timeout period (t reset ) and then goes high. this device also asserts enable if three consecutive watch - dog timeout periods have elapsed without a falling edge at wdi. enable remains low until three consecutive wdi falling edges with periods shorter than the watchdog time - out period occur (see figure 2 ). the internal watchdog timer is cleared by a reset rising edge or by a falling edge at wdi. the watchdog timer remains cleared while reset is asserted; as soon as reset is released, the timer starts counting. wdi falling edges are ignored when reset is low. if no wdi falling edge occurs within the watchdog timeout period, reset immediately goes low and stays low for the adjusted reset timeout period. max16998b/d the max16998b/d have a windowed watchdog timer. the watchdog timeout period (t wp ) is the sum of a closed window period (t cw ) and an open window period (t ow ). if the c issues a wdi falling edge within the open win - dow period, reset stays high. once a wdi falling edge occurs within the closed window period, reset immedi - ately goes low and stays low for the adjusted reset time - out period (see figure 3 ). if no wdi falling edge occurs within the watchdog timeout period, reset immediately goes low and stays low for the adjusted reset timeout period. the open window size is factory-set to 50% of the watchdog timeout period for the max16998b and 75% for the max16998d. figure 8 shows a wdi falling edge identified as a good or a bad wdi signal edge. in case 1, the wdi falling edge occurs within the closed window period and is considered a bad wdi falling edge (early fault); therefore, it asserts reset . case 2 also shows another fault. in this case, figure 7. setting resetin voltage for the max16998a/b/d max16998a/b/d resetin v in v cc r1 r2 max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 11 downloaded from: http:///
no wdi falling edge occurs within the watchdog timeout period (t wp ) and is considered a late fault that asserts reset . in case 3, the wdi falling edge occurs within the open window period and is considered a good wdi sig - nal falling edge. in this case, reset stays high. in case 4, the wdi falling edge occurs within the indeterminate region. in this case, the reset state is indeterminate. these devices assert enable after three consecutive bad wdi falling edges. enable returns high after three consecutive good wdi signal falling edges (see figure 3 ). either a rising edge at reset or a falling edge at wdi clears the internal watchdog timer. the watchdog timer remains cleared while reset is asserted. the watchdog timer begins counting when reset goes high. wdi fall - ing edges are ignored when reset is low. applications information selecting the reset timeout capacitor the reset timeout period is adjustable to accommodate a variety of p applications. adjust the reset timeout period (t reset ) by connecting a capacitor (c srt ) between srt and ground. see the reset timeout period vs. c srt graph in the typical operating characteristics section . calculate the reset timeout capacitance using the equation below: ramp srt reset ramp i ct v = where v ramp is in volts, t reset is in seconds, i ramp is in na, and c srt is in nf. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at srt may cause errors in the reset timeout period. if precise time control is required, use capacitors with low leakage current and high stability. selecting the watchdog timeout capacitor the watchdog timeout period is adjustable to accommodate a variety of p applications. with this feature, the watchdog timeout can be optimized for software execution. the pro - grammer determines how often the watchdog timer should be serviced. adjust the watchdog timeout period (t wp ) by connecting a capacitor (c swt ) between swt and gnd. for normal mode operation, calculate the watchdog timeout capacitance using the following equation: ramp swt wp ramp i ct 4v = where v ramp is in volts, t wp is in seconds, i ramp is in na, and c swt is in nf. see the watchdog timeout period vs. c swt graph in the typical operating characteristics section . for the max16998b/max16998d, the open window size is factory-set to 50% (max16998b) or 75% (max16998d) of the watchdog period. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at swt may cause errors in the watchdog timeout period. if precise time control is required, use capacitors with low figure 8. the max16998b/d window watchdog diagram t wdimin reset rising edge t wdimax t wp (50% or 75%) x t wp case 1 (fast fault)case 2 (slow fault) case 3 (good wdi) case 4 (indeterminate) closed window open window indeterminate max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 12 downloaded from: http:///
leakage current and high stability. to disable the watchdog timer function, connect swt to ground and connect wdi to either the high- or low-logic state. interfacing to other voltages for logic compatibility as shown in figure 9 , the open-drain reset output can operate in the 2.5v to 18v range. this allows the device to interface a p with other logic levels. wdi glitch immunity for additional glitch immunity, connect an rc lowpass filter as close as possible to wdi (see figure 10 ). for example, for glitches with duration of 1s, a 12k resistor and a 47pf capacitor will provide immunity. layout considerations srt and swt are connected to internal precision current sources. when developing the layout for the application, minimize stray capacitance attached to srt and swt as well as leakage currents that can reach those nodes. srt and swt traces should be as short as possible. route traces carrying high-speed digital signals and traces with large voltage potentials as far from srt and swt as possible. leakage currents and stray capacitance (e.g., a scope probe, which induces both) at these pins may cause errors in the reset and/or watchdog timeout period. when evaluating these parts, use clean prototype boards to ensure accurate reset and watchdog timeout periods. resetin is a high-impedance input and a high-imped - ance resistive divider (e.g., 100k to 1m) sets the threshold level. minimize coupling to transient signals by keeping the connections to this input short. any dc leakage current at resetin (e.g., a scope probe) causes errors in the programmed reset threshold. typical operating circuits reset remains asserted as long as resetin is below the regulated voltage and for the reset timeout period after resetin goes high to assure that the monitored ldo voltage is settled. then, the c starts operating and triggers wdi. if the c fails to operate correctly (e.g., the software execution is stuck in a loop), the wdi signal does not trigger the watchdog timer any more, and reset is pulled low, resetting the c. if the c does not work properly in the next loop either, the device asserts reset again. after three watchdog timeout periods with no wdi falling edges, enable asserts and flags backup or safety circuits that take over the operation. figure 9. interfacing to other voltage levels figure 10. additional wdi glitch immunity circuit max16998a/b/d reset reset gnd gnd 5v to 40v 2.5v to 18v in v cc p n 10k ? max16998a/b/d wdi i/o gnd gnd in v cc r c p max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 13 downloaded from: http:///
figure 11. max16998a/b/d switch over to backup circuitry figure 12. max16997a application diagram max16998a/b/d enable en reset srt backup circuitry, peripheral 5v regulator resetinswt gnd in v batt v cc v cc r1 r2 reset i/o gnd c wdi max16997a enable reset 5v backup circuitry, peripheral backup circuitry flags separatewatchdog enswt gnd in v batt v cc r1 r2 watchdog ldo 5v regulator i/o gnd mc i/o wdi max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 14 downloaded from: http:///
package type package code outline no. land pattern no. 8 max u8+1, u8+4 21-0036 90-0092 top view 12 34 8 7 6 5 enable n.c. wdignd swt n.c. en in max16997a max + 12 34 8 7 6 5 enable reset wdignd swt srt resetin in max16998a/b/d max + max16997/max16998 high-voltage watchdog timers with adjustable timeout delay www.maximintegrated.com maxim integrated 15 pin conigurations package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos downloaded from: http:///
revision number revision date description pages changed 0 2/08 initial release 1 4/09 added bullet to features section, revised electrical characteristics table 1, 2, 3 2 8/09 added automotive qualiied parts 1 3 11/15 updated package code and rebranded data sheet 15 4 3/16 deleted max16997aaua/v+ variant from ordering information 1 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2016 maxim integrated products, inc. 16 max16997/max16998 high-voltage watchdog timers with adjustable timeout delay revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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